Assembly Code Optimization - Revision history

Exophase: /* NEON */

2016-04-30T18:58:37Z

‎NEON

2016-04-30T18:58:25Z

‎NEON

2016-04-30T18:57:49Z

Added NEON load-hit-store penalties and misaligned access caveat

2016-04-30T17:41:51Z

‎NEON

2016-04-30T17:39:12Z

‎NEON

2016-04-30T17:14:08Z

2011-04-19T17:57:43Z

links

2011-04-19T14:21:10Z

‎Code alignment: cat

2011-04-19T13:41:45Z

‎Code alignment: cat

2010-11-12T12:58:42Z

‎Instruction pairing restrictions following a branch: Remove somewhat inaccurate statement

@@ Line 56: / Line 56: @@
    bne loop
-If 0 is unaligned, the next iteration of vld1.u32 will overlap with the previous iteration of vst1.u32, which will cause a stall. To avoid this situation you can reorder the loop so that the store happens one element behind.
+If r0 is unaligned, the next iteration of vld1.u32 will overlap with the previous iteration of vst1.u32, which will cause a stall. To avoid this situation you can reorder the loop so that the store happens one element behind.
 [[Category:Development]]
 [[Category:Optimization]]
 [[Category:Chipset]]

@@ Line 49: / Line 49: @@
 You should avoid any NEON loads that come from a location that has recently been written to. NEON does not have store forwarding, so this can cost dozens of cycles. This can happen unknowingly if you use unaligned loads, because they're performed with two aligned accesses. For example, if you have this sequence:
-loop:
+ loop:
    vld1.u32 { q0 }, [r0]
    vadd.u32 q0, q0, q1
    vst1.u32 { q0 }, [r0]!
    subs r1, #1
    bne loop

@@ Line 46: / Line 46: @@
 Even though the VFP is not pipelined, the VFP vldr instructions are. "vldr s0, [r0]" will be faster than "vld1.32 {d0[0]}, [r0]" (2 vs 3 cycles, vldr also gives more flexible addressing mode). The same can't be said about "vmov sX, sY", it waits for all previous instructions to complete before issuing.
 [[Category:Development]]
 [[Category:Optimization]]
 [[Category:Chipset]]

@@ Line 42: / Line 42: @@
 As the manual states, passing data from NEON (and VFP) back to ARM takes at least 20 cycles, but there are some tricks that can be used. The vmov instruction itself that is passing the data will not cause any stalls (provided the needed NEON register is already available), the stall will actually happen on any ARM instruction that follows instead (including branches). This means that:
 * Multiple "vmov.32 rX, dY[Z]" can be done back-to-back and only incur one stall after the whole sequence
-* Additional NEON instructions can be issued after "vmov" without stalls (with enough instructions the stall can be completely avoided)
+* Additional NEON instructions can be issued after "vmov" without stalling (with enough instructions the stall can be completely avoided)
 * Additional unrelated NEON instructions can be issued before "vmov" (to hide the latency of instruction that produces the source register data)

@@ Line 41: / Line 41: @@
 == NEON ==
 As the manual states, passing data from NEON (and VFP) back to ARM takes at least 20 cycles, but there are some tricks that can be used. The vmov instruction itself that is passing the data will not cause any stalls (provided the needed NEON register is already available), the stall will actually happen on any ARM instruction that follows instead (including branches). This means that:
-* Multiple "vmov.32 rX, dY[Z]" can be done back-to-back and only have one stall after the whole sequence
+* Multiple "vmov.32 rX, dY[Z]" can be done back-to-back and only incur one stall after the whole sequence
-* Additional NEON instructions can be issued after "vmov" without stalls (with enough instructions the stall can be hidden completely)
+* Additional NEON instructions can be issued after "vmov" without stalls (with enough instructions the stall can be completely avoided)
 * Additional unrelated NEON instructions can be issued before "vmov" (to hide the latency of instruction that produces the source register data)

@@ Line 1: / Line 1: @@
 == Assembly code optimization on the Cortex-A8 ==
-This guide presents specific optimization techniques for the ARM Cortex-A8 processor and its dual-issue, in-order pipeline.
+This guide presents specific optimization techniques for the [[ARM]] Cortex-A8 processor and its dual-issue, in-order pipeline.
 == Use the ARMv7 movw/movt instructions ==

← Older revision		Revision as of 12:58, 12 November 2010
Line 33:		Line 33:

	Flag-setting instructions can be used to avoid this restriction. Additionally, MOV instructions that do not have immediate values can be replaced with ADD, SUB, ORR, or EOR instructions using zero as an immediate value.		Flag-setting instructions can be used to avoid this restriction. Additionally, MOV instructions that do not have immediate values can be replaced with ADD, SUB, ORR, or EOR instructions using zero as an immediate value.
−
−	One exception to this rule is that placing such an instruction (eg mov r0,r0) following an unconditional branch may reduce the severity of a misprediction, due to the second instruction possibly being incorrectly predicted as a branch, but resulting in the correct target being retrieved from the BTB.

	== Code alignment ==		== Code alignment ==